> Axelera's chips follow a similar formula as other AI ASICs, such as Google's tensor processing units. The Dutch outfit's current silicon feature four accelerator cores, each with a matrix multiply-accumulate (MAC) unit, a RISC-V control core to make the accelerator programmable, and some digital signal processors which handle neural network activation functions.

This seems very focused on current architecture, which could be replaced with something more novel without the fundamental limits of matrix multiplication.