As a teaching tool RISC-V is clearly great, as it is for companies that want to add custom instructions to their microcontrollers like NVidia or WD. But if I was looking to design a core to run user applications then to me it looks like everything is stacked in favor of Power. The complexity of the ISA is dwarfed by the complexity of a performant superscalar architecture. And to be performant in RISC-V you'd probably be needing extensive instruction fusion and variable length instructions anyways further equalizing things. And you really need the B extension which hasn't been standardized yet. Plus binary compatibility is a big concern on application cores and ISA extensions get in the way of that.