NAND always has at least one or two layers of ECC protecting your data, so deliberately induced read disturb errors are a lot harder to turn into a practical exploit—and that's before adding any specific measures to predict and prevent read disturb errors.
I used to work in SSD firmware development. Thing is the newer generations of NAND are quite fragile so the ECC protection is essential and it is a lot easier to trigger read disturb since you can issue millions of reads with ease. Of course various caches in the controller and system can mitigate the trivial access patterns. With read disturb detection algorithms the difficulty is you would need lots of fine grain access statistics to make it optimal.
