There are tons of other practical problems. The HLS generated verilog is name mangled. This makes it really hard to generate all the various control files you need to run the EDA flow, the software that assists in turning verilog into manufacturing files. If you have a super stable design, like a codec, then you can deal with it because it’s basically a waterfall development cycle. But if you have a design whose requirements are changing as you develop it, like most things. HLS doesn’t fit into the existing organizational structures and you’ll end up with a less optimal circuit.
This is not true for SpinalHDL and Amaranth/migen (I can’t speak about Chisel): the names of registers and IO ports are totally predictable and there’s no issues generation timing constraints, placement constraints etc.
If our backend team doesn’t complain about HLS, it most certainly won’t complain about RTL generators.
FWIW: the codecs are not super stable designs at all. They’re under constant development.
For modern ASICs, layout partitions are so large that your backend tools see hundreds of thousands of instances that are on the same clocks. The synthesis tools may have special recipes for optimization (which, again, you can still do), but the backend flow is mostly concerned with meeting timing on that clock. Except for external IOs, it’s rare to have specialty timing constraints at within partitions.
I think this comes from the idea that running the EDA flow is like compiling software and that’s the problem, it’s not.
The EDA flow, the software that goes from verilog to manufacturable files, is electrical engineering. Sure, it’s heavily automated, but it’s not fully automated. And if you want a semi decent chip, the tools need a ton of hand holding. And if you want a great chip, get prepared to dig into all the intermediate files…
If you just want a chip, any chip, they can kinda give you that in a fully automated way.
You’re preaching to the choir on improving validation. Like you mentioned, In commercial designs that’s where a majority of the man hours actually go, and coincidentally where basically none go in academia where chisel is popular.
I will mention though, not all IP needs max PPA or specific control of the netlist and there could be initial opportunities there. Especially with the cost per area on many nodes going significantly down it can be more economical, at some volumes, to save man hours with HLS even if it leads to larger areas, which in theory means more production cost but in reality might not even change the floor plan.
The funny thing is these effing boomers still protest against nuclear power at the end of University Avenue every month, as if this was somehow a relevant concern in 2023.
I remember when I lived there, they had to get a special exemption to use self-checkout machines made by 3M in the Berkeley library. I don't remember why 3M ended up on the bad boy list, probably something related to nuclear weapons though.
"The Peace and Justice Commission finds that it would violate the Nuclear Free Berkeley Act (NFBA) to approve a waiver of the law and contract with 3M Corporation for maintenance of the Library’s RFID system."
"Pursuant to B.M.C. Section 12.90.070, the City of Berkeley shall grant no contract to any person or business, which knowingly engages in work for nuclear weapons."
